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ds025-3 (v2.3.2) march 14, 2003 www.xilinx.com module 3 of 4 1-800-255-7778 1 ? 2000-2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. virtex-e extended memory electrical characteristics definition of terms electrical and switching characteristics are specified on a per-speed-grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance : these speed files are based on simulations only and are typically available soon after device design specifi- cations are frozen. although speed grades with this desig- nation are considered relatively stable and conservative, some under-reporting might still occur. preliminary : these speed files are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of unde r-reporting delays is greatly reduced as compared to advance data. production : these speed files are released once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typ- ically, the slowest speed grades transition to production before faster speed grades. all specifications are representative of worst-case supply voltage and junction temperature conditions. the parame- ters included are common to popular designs and typical applications. contact the factory for design considerations requiring more detailed information. ta ble 1 correlates the current status of each virtex-e extended memory device with a corresponding speed file designation. all specifications are subject to change without notice. dc characteristics absolute maximum ratings 0 virtex?-e 1.8 v extended memory field programmable gate arrays ds025-3 (v2.3.2) march 14, 2003 00 production product specification r ta ble 1 : virtex-e extended memory device speed grade designations device speed grade designations advance preliminary production xcv405e ?8, ?7, ?6 xcv812e ?8, ?7, ?6 symbol description (1) units v ccint internal supply voltage relative to gnd ? 0.5 to 2.0 v v cco supply voltage relative to gnd ? 0.5 to 4.0 v v ref input reference voltage ? 0.5 to 4.0 v v in (3) input voltage relative to gnd ? 0.5 to v cco +0.5 v v ts voltage applied to 3-state output ? 0.5 to 4.0 v v cc longest supply voltage rise time from 0 v ? 1.71 v 50 ms t stg storage temperature (ambient) ? 65 to +150 c t j junction temperature (2) plastic packages +125 c notes: 1. stresses beyond those listed under absolute maximum ratings can cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time can affect device reliability. 2. for soldering guidelines and thermal considerations, see the device packaging information on www.xilinx.com . 3. inputs configured as pci are fully pci compliant. this statement takes precedence over any specification that would imply tha t the device is not pci compliant.
virtex ? -e 1.8 v extended memory field programmable gate arrays module 3 of 4 www.xilinx.com ds025-3 (v2.3.2) march 14, 2003 2 1-800-255-7778 r recommended operating conditions dc characteristics over recommended operating conditions power-on power supply requirements xilinx fpgas require a certain amount of supply current during power-on to insure proper device operation. the actual current consumed depends on the power-on ramp rate of the power supply. this is the time required to reach the nominal power supply voltage of the device 1 from 0 v. the fastest ramp rate is 0 v to nominal voltage in 2 ms and the slowest allowed ramp rate is 0 v to nominal voltage in 50 ms. for more details on power supply requirements, see xapp158 on www.xilinx.com . symbol description min max units v ccint internal supply voltage relative to gnd, t j = 0 c to +85 c commercial 1.8 ? 5% 1.8 + 5% v internal supply voltage relative to gnd, t j = ? 40 c to +100 c industrial 1.8 ? 5% 1.8 + 5% v v cco supply voltage relative to gnd, t j = 0 c to +85 c commercial 1.2 3.6 v supply voltage relative to gnd, t j = ? 40 c to +100 c industrial 1.2 3.6 v t in input signal transition time 250 ns symbol description (1) device min max units v drint data retention v ccint vo lta ge (below which configuration data might be lost) all 1.5 v v drio data retention v cco voltage (below which configuration data might be lost) all 1.2 v i ccintq quiescent v ccint supply current 1 xcv405e 400 ma xcv812e 500 ma i ccoq quiescent v cco supply current 1 xcv405e 2 ma xcv812e 2 ma i l input or output leakage current all ? 10 +10 a c in input capacitance (sample tested) bga, pq, hq, packages all 8 pf i rpu pad pull-up (when selected) @ v in = 0 v, v cco = 3.3 v (sample tested) all note 2 0.25 ma i rpd pad pull-down (when selected) @ v in = 3.6 v (sample tested) note 2 0.25 ma notes: 1. with no output current loads, no active input pull-up resistors, all i/o pins 3-stated and floating. 2. internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. these pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. product (commercial grade) description (2) current requirement (3) xcv50e - xcv600e minimum required current supply 500 ma xcv812e - xcv2000e minimum required current supply 1 a xcv2600e - xcv3200e minimum required current supply 1.2 a virtex-e family, industrial grade minimum required current supply 2 a notes: 1. ramp rate used for this specification is from 0 - 1.8 v dc. peak current occurs on or near the internal power-on reset thresho ld and lasts for less than 3 ms. 2. devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above. 3. larger currents might result if ramp rates are forced to be faster.
virtex ? -e 1.8 v extended memory field programmable gate arrays ds025-3 (v2.3.2) march 14, 2003 www.xilinx.com module 3 of 4 1-800-255-7778 3 r dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. input/output standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lv t t l (1) ? 0.5 0.8 2.0 3.6 0.4 2.4 24 ? 24 lv c m o s 2 ? 0.5 0.7 1.7 2.7 0.4 1.9 12 ? 12 lv c m o s 1 8 ? 0.5 20% v cco 70% v cco 1.95 0.4 v cco ? 0.4 8 ? 8 pci, 3.3 v ? 0.5 30% v cco 50% v cco v cco + 0.5 10% v cco 90% v cco note 2 note 2 gtl ? 0.5 v ref ? 0.05 v ref + 0.05 3.6 0.4 n/a 40 n/a gtl+ ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.6 n/a 36 n/a hstl i (3) ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 8 ? 8 hstl iii ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 24 ? 8 hstl iv ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 48 ? 8 sstl3 i ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.6 v ref + 0.6 8 ? 8 sstl3 ii ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.8 v ref + 0.8 16 ? 16 sstl2 i ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.61 v ref + 0.61 7.6 ? 7.6 sstl2 ii ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.80 v ref + 0.80 15.2 ? 15.2 ctt ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.4 v ref + 0.4 8 ? 8 agp ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 10% v cco 90% v cco note 2 note 2 notes: 1. v ol and v oh for lower drive currents are sample tested. 2. tested according to the relevant specifications. 3. dc input and output levels for hstl18 (hstl i/o standard with v cco of 1.8 v) are provided in an hstl white paper on www.xilinx.com .
virtex ? -e 1.8 v extended memory field programmable gate arrays module 3 of 4 www.xilinx.com ds025-3 (v2.3.2) march 14, 2003 4 1-800-255-7778 r lvds dc specifications lvpecl dc specifications these values are valid at the output of the source termination pack shown under lv pe c l , with a 100 ? differential load only. the v oh levels are 200 mv below standard lvpecl levels and are compatible with devices tolerant of lower common-mode ranges. the following table summarizes the dc output specifications of lvpecl. dc parameter symbol conditions min typ max units supply voltage v cco 2.375 2.5 2.625 v output high voltage for q and q v oh r t = 100 ? across q and q signals 1.25 1.425 1.6 v output low voltage for q and q v ol r t = 100 ? across q and q signals 0.9 1.075 1.25 v differential output voltage (q ? q ), q = high (q ? q), q = high v odiff r t = 100 ? across q and q signals 250 350 450 mv output common-mode voltage v ocm r t = 100 ? across q and q signals 1.125 1.25 1.375 v differential input voltage (q ? q ), q = high (q ? q), q = high v idiff common-mode input voltage = 1.25 v 100 350 na mv input common-mode voltage v icm differential input voltage = 350 mv 0.2 1.25 2.2 v notes: 1. refer to the design consideration section for termination schematics. dc parameter min max min max min max units v cco 3.0 3.3 3.6 v v oh 1.8 2.11 1.92 2.28 2.13 2.41 v v ol 0.96 1.27 1.06 1.43 1.30 1.57 v v ih 1.49 2.72 1.49 2.72 1.49 2.72 v v il 0.86 2.125 0.86 2.125 0.86 2.125 v differential input voltage 0.3 - 0.3 - 0.3 - v
virtex ? -e 1.8 v extended memory field programmable gate arrays ds025-3 (v2.3.2) march 14, 2003 www.xilinx.com module 3 of 4 1-800-255-7778 5 r virtex-e switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all virtex-e devices unless otherwise noted. iob input switching characteristics input delays associated with the pad are specified for lvttl levels. for other standards, adjust the delays with the values shown in ?? iob input switching characteristics standard adjustments ?? on page 6 . speed grade (2) units description (1) symbol device min -8 -7 -6 propagation delays pad to i output, no delay t iopi all 0.43 0.8 0.8 0.8 ns, max pad to i output, with delay t iopid xcv405e 0.51 1.0 1.0 1.0 ns, max xcv812e 0.55 1.1 1.1 1.1 ns, max pad to output iq via transparent latch, no delay t iopli all 0.75 1.4 1.5 1.6 ns, max pad to output iq via transparent latch, with delay t ioplid xcv405e 1.55 3.5 3.6 3.7 ns, max xcv812e 1.55 3.5 3.6 3.7 ns, max propagation delays clock minimum pulse width, high t ch all 0.56 1.2 1.3 1.4 ns, min minimum pulse width, low t cl 0.56 1.2 1.3 1.4 ns, min clock clk to output iq t iockiq 0.18 0.4 0.7 0.7 ns, max setup and hold times with respect to clock at iob input register pad, no delay t iopick / t ioickp all 0.69 / 0 1.3 / 0 1.4 / 0 1.5 / 0 ns, min pad, with delay t iopickd / t ioickpd xcv405e 1.49 / 0 3.4 / 0 3.5 / 0 3.5 / 0 ns, min xcv812e 1.49 / 0 3.4 / 0 3.5 / 0 3.5 / 0 ns, min ice input t ioiceck / t iockice all 0.28 / 0.0 0.55 / 0.01 0.7 / 0.01 0.7 / 0.01 ns, min sr input (iff, synchronous) t iosrcki all 0.38 0.8 0.9 1.0 ns, min set/reset delays sr input to iq (asynchronous) t iosriq all 0.54 1.1 1.2 1.4 ns, max gsr to output iq t gsrq all 3.88 7.6 8.5 9.7 ns, max notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time. 2. input timing i for lvttl is measured at 1.4 v. for other i/o standards, see table 3 .
virtex ? -e 1.8 v extended memory field programmable gate arrays module 3 of 4 www.xilinx.com ds025-3 (v2.3.2) march 14, 2003 6 1-800-255-7778 r iob input switching characteristics standard adjustments i speed grade (1) units description symbol standard min -8 -7 -6 data input delay adjustments standard-specific data input delay adjustments t ilvttl lvttl 0.0 0.0 0.0 0.0 ns t ilvcmos2 lvc m o s2 ? 0.02 0.0 0.0 0.0 ns t ilvcmos18 lv c m os 18 ? 0.02 +0.20 +0.20 +0.20 ns t ilvds lvds 0.00 +0.15 +0.15 +0.15 ns t ilvpecl lvpecl 0.00 +0.15 +0.15 +0.15 ns t ipci33_3 pci, 33 mhz, 3.3 v ? 0.05 +0.08 +0.08 +0.08 ns t ipci66_3 pci, 66 mhz, 3.3 v ? 0.05 ? 0.11 ? 0.11 ? 0.11 ns t igtl gtl +0.10 +0.14 +0.14 +0.14 ns t igtlplus gtl+ +0.06 +0.14 +0.14 +0.14 ns t ihstl hstl +0.02 +0.04 +0.04 +0.04 ns t isstl2 sstl2 ? 0.04 +0.04 +0.04 +0.04 ns t isstl3 sstl3 ? 0.02 +0.04 +0.04 +0.04 ns t ictt ctt +0.01 +0.10 +0.10 +0.10 ns t iagp agp ? 0.03 +0.04 +0.04 +0.04 ns notes: 1. input timing i for lvttl is measured at 1.4 v. for other i/o standards, see table 3 . figure 1: virtex-e input/output block (iob) obuft ibuf vref ds022_02_091300 sr clk ice oce o i iq t t ce d ce q sr d ce q sr d ce q sr pad programmable delay weak keeper
virtex ? -e 1.8 v extended memory field programmable gate arrays ds025-3 (v2.3.2) march 14, 2003 www.xilinx.com module 3 of 4 1-800-255-7778 7 r iob output switching characteristics, figure 1 output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays with the values shown in ?? iob output switching characteristics standard adjustments ?? on page 8 .. speed grade (2) units description (1) symbol min 3 -8 -7 -6 propagation delays o input to pad t ioop 1.04 2.5 2.7 2.9 ns, max o input to pad via transparent latch t ioolp 1.24 2.9 3.1 3.4 ns, max 3-state delays t input to pad high-impedance (note 2) t iothz 0.73 1.5 1.7 1.9 ns, max t input to valid data on pad t ioton 1.13 2.7 2.9 3.1 ns, max t input to pad high-impedance via transparent latch (note 2) t iotlphz 0.86 1.8 2.0 2.2 ns, max t input to valid data on pad via transparent latch t iotlpon 1.26 3.0 3.2 3.4 ns, max gts to pad high impedance (note 2) t gts 1.94 4.1 4.6 4.9 ns, max sequential delays clock clk minimum pulse width, high t ch 0.56 1.2 1.3 1.4 ns, min minimum pulse width, low t cl 0.56 1.2 1.3 1.4 ns, min clock clk to pad t iockp 0.97 2.4 2.8 2.9 ns, max clock clk to pad high-impedance (synchronous) (note 2) t iockhz 0.77 1.6 2.0 2.2 ns, max clock clk to valid data on pad (synchronous) t iockon 1.17 2.8 3.2 3.4 ns, max setup and hold times before/after clock clk o input t ioock / t iocko 0.43 / 0 0.9 / 0 1.0 / 0 1.1 / 0 ns, min oce input t iooceck / t iockoce 0.28 / 0 0.55 / 0.01 0.7 / 0 0.7 / 0 ns, min sr input (off) t iosrcko / t iockosr 0.40 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min 3-state setup times, t input t iotck / t iockt 0.26 / 0 0.51 / 0 0.6 / 0 0.7 / 0 ns, min 3-state setup times, tce input t iotceck / t iocktce 0.30 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min 3-state setup times, sr input (tff) t iosrckt / t iocktsr 0.38 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min set/reset delays sr input to pad (asynchronous) t iosrp 1.30 3.1 3.3 3.5 ns, max sr input to pad high-impedance (asynchronous) (note 2) t iosrhz 1.08 2.2 2.4 2.7 ns, max sr input to valid data on pad (asynchronous) t iosron 1.48 3.4 3.7 3.9 ns, max gsr to pad t iogsrq 3.88 7.6 8.5 9.7 ns, max notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time. 2. 3-state turn-off delays should not be adjusted.
virtex ? -e 1.8 v extended memory field programmable gate arrays module 3 of 4 www.xilinx.com ds025-3 (v2.3.2) march 14, 2003 8 1-800-255-7778 r iob output switching characteristics standard adjustments output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays by the values shown. speed grade units description symbol standard min -8 -7 -6 output delay adjustments standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, csl) t olvttl_s2 lvttl, slow, 2 ma 4.2 +14.7 +14.7 +14.7 ns t olvttl_s4 4 ma 2.5 +7.5 +7.5 +7.5 ns t olvttl_s6 6 ma 1.8 +4.8 +4.8 +4.8 ns t olvttl_s8 8 ma 1.2 +3.0 +3.0 +3.0 ns t olvttl_s12 12 ma 1.0 +1.9 +1.9 +1.9 ns t olvttl_s16 16 ma 0.9 +1.7 +1.7 +1.7 ns t olvttl_s24 24 ma 0.8 +1.3 +1.3 +1.3 ns t olvttl_f2 lvttl, fast, 2 ma 1.9 +13.1 +13.1 +13.1 ns t olvttl_f4 4 ma 0.7 +5.3 +5.3 +5.3 ns t olvttl_f6 6 ma 0.20 +3.1 +3.1 +3.1 ns t olvttl_f8 8 ma 0.10 +1.0 +1.0 +1.0 ns t olvttl_f12 12 ma 0.0 0.0 0.0 0.0 ns t olvttl_f16 16 ma ? 0.10 ? 0.05 ? 0.05 ? 0.05 ns t olvttl_f24 24 ma ? 0.10 ? 0.20 ? 0.20 ? 0.20 ns t olvcmos_2 lv c m os 2 0.10 +0.09 +0.09 +0.09 ns t olvcmos_18 lv c m o s 1 8 0.10 +0.7 +0.7 +0.7 ns t olvds lv d s ? 0.39 ? 1.2 ? 1.2 ? 1.2 ns t olvpecl lv pe c l ? 0.20 ? 0.41 ? 0.41 ? 0.41 ns t opci33_3 pci, 33 mhz, 3.3 v 0.50 +2.3 +2.3 +2.3 ns t opci66_3 pci, 66 mhz, 3.3 v 0.10 ? 0.41 ? 0.41 ? 0.41 ns t ogtl gtl 0.6 +0.49 +0.49 +0.49 ns t ogtlp gtl+ 0.7 +0.8 +0.8 +0.8 ns t ohstl_i hstl i 0.10 ? 0.51 ? 0.51 ? 0.51 ns t ohstl_iiii hstl iii ? 0.10 ? 0.91 ? 0.91 ? 0.91 ns t ohstl_iv hstl iv ? 0.20 ? 1.01 ? 1.01 ? 1.01 ns t osstl2_i sstl2 i ? 0.10 ? 0.51 ? 0.51 ? 0.51 ns t osstl2_ii sstl2 ii ? 0.20 ? 0.91 ? 0.91 ? 0.91 ns t osstl3_i sstl3 i ? 0.20 ? 0.51 ? 0.51 ? 0.51 ns t osstl3_ii sstl3 ii ? 0.30 ? 1.01 ? 1.01 ? 1.01 ns t octt ctt 0.0 ? 0.61 ? 0.61 ? 0.61 ns t oagp agp ? 0.1 ? 0.91 ? 0.91 ? 0.91 ns
virtex ? -e 1.8 v extended memory field programmable gate arrays ds025-3 (v2.3.2) march 14, 2003 www.xilinx.com module 3 of 4 1-800-255-7778 9 r calculation of t ioop as a function of capacitance t ioop is the propagation delay from the o input of the iob to the pad. the values for t ioop are based on the standard capacitive load (csl) for each i/o standard as listed in ta bl e 2 . for other capacitive loads, use the formulas below to calcu- late the corresponding t ioop . t ioop = t ioop + t opadjust + (c load ? c sl ) * fl where: t opadjust is reported above in the output delay adjustment section. c load is the capacitive load for the design. table 2: constants for use in calculation of t ioop standard csl (pf) fl (ns/pf) lvttl fast slew rate, 2ma drive 35 0.41 lvttl fast slew rate, 4ma drive 35 0.20 lvttl fast slew rate, 6ma drive 35 0.13 lvttl fast slew rate, 8ma drive 35 0.079 lvttl fast slew rate, 12ma drive 35 0.044 lvttl fast slew rate, 16ma drive 35 0.043 lvttl fast slew rate, 24ma drive 35 0.033 lvttl slow slew rate, 2ma drive 35 0.41 lvttl slow slew rate, 4ma drive 35 0.20 lvttl slow slew rate, 6ma drive 35 0.10 lvttl slow slew rate, 8ma drive 35 0.086 lvttl slow slew rate, 12ma drive 35 0.058 lvttl slow slew rate, 16ma drive 35 0.050 lvttl slow slew rate, 24ma drive 35 0.048 lv c m o s 2 3 5 0 . 0 4 1 lvcmos18 35 0.050 pci 33 mhz 3.3 v 10 0.050 pci 66 mhz 3.3 v 10 0.033 gtl 0 0.014 gtl+ 0 0.017 hstl class i 20 0.022 hstl class iii 20 0.016 hstl class iv 20 0.014 sstl2 class i 30 0.028 sstl2 class ii 30 0.016 sstl3 class i 30 0.029 sstl3 class ii 30 0.016 ctt 20 0.035 agp 10 0.037 notes: 1. i/o parameter measurements are made with the capacitance values shown above. see the application examples for appropriate terminations. 2. i/o standard measurements are reflected in the ibis model information except where the ibis format precludes it. ta ble 3 : delay measurement methodology standard v l 1 v h 1 meas. point v ref (typ) 2 lvttl 031.4- lv c m o s 2 02.51.125- pci33_3 per pci spec - pci66_3 per pci spec - gtl v ref ? 0.2 v ref +0.2 v ref 0.80 gtl+ v ref ? 0.2 v ref +0.2 v ref 1.0 hstl class i v ref ? 0.5 v ref +0.5 v ref 0.75 hstl class iii v ref ? 0.5 v ref +0.5 v ref 0.90 hstl class iv v ref ? 0.5 v ref +0.5 v ref 0.90 sstl3 i & ii v ref ? 1.0 v ref +1.0 v ref 1.5 sstl2 i & ii v ref ? 0.75 v ref +0.75 v ref 1.25 ctt v ref ? 0.2 v ref +0.2 v ref 1.5 agp v ref ? (0.2xv cco ) v ref + (0.2xv cco ) v ref per agp spec lv d s 1.2 ? 0.125 1.2 + 0.125 1.2 lvpecl 1.6 ? 0.3 1.6 + 0.3 1.6 notes: 1. input waveform switches between v l and v h . 2. measurements are made at v ref (typ), maximum, and minimum. worst-case values are reported. i/o parameter measurements are made with the capacitance values shown in ta bl e 2 . see the application examples for appropriate terminations. i/o standard measurements are reflected in the ibis model information except where the ibis format precludes it.
virtex ? -e 1.8 v extended memory field programmable gate arrays module 3 of 4 www.xilinx.com ds025-3 (v2.3.2) march 14, 2003 10 1-800-255-7778 r clock distribution switching characteristics i/o standard global clock input adjustments description symbol speed grade units min-8-7-6 gclk iob and buffer global clock pad to output. t gpio 0.38 0.7 0.7 0.7 ns, max global clock buffer i input to o output t gio 0.11 0.19 0.45 0.50 ns, max description (1) symbol standard speed grade units min-8-7-6 data input delay adjustments standard-specific global clock input delay adjustments t gplvttl lvttl 0.0 0.0 0.0 0.0 ns, max t gplvcmos2 lv c m os 2 ? 0.02 0.0 0.0 0.0 ns, max t gplvcmos18 lvcmos2 0.12 0.20 0.20 0.20 ns, max t glvds lvds 0.23 0.38 0.38 0.38 ns, max t glvpecl lvpecl 0.23 0.38 0.38 0.38 ns, max t gppci33_3 pci, 33 mhz, 3.3 v ? 0.05 0.08 0.08 0.08 ns, max t gppci66_3 pci, 66 mhz, 3.3 v ? 0.05 ? 0.11 ? 0.11 ? 0.11 ns, max t gpgtl gtl 0.20 0.37 0.37 0.37 ns, max t gpgtlp gtl+ 0.20 0.37 0.37 0.37 ns, max t gphstl hstl 0.18 0.27 0.27 0.27 ns, max t gpsstl2 sstl2 0.21 0.27 0.27 0.27 ns, max t gpsstl3 sstl3 0.18 0.27 0.27 0.27 ns, max t gpctt ctt 0.22 0.33 0.33 0.33 ns, max t gpagp agp 0.21 0.27 0.27 0.27 ns, max notes: 1. input timing for gplvttl is measured at 1.4 v. for other i/o standards, see ta b l e 3 .
virtex ? -e 1.8 v extended memory field programmable gate arrays ds025-3 (v2.3.2) march 14, 2003 www.xilinx.com module 3 of 4 1-800-255-7778 11 r clb switching characteristics delays originating at f/g inputs vary slightly according to the input used, see figure 2 . the values listed below are worst-case. precise values are provided by the timing analyzer. description (1) symbol speed grade units min -8 -7 -6 combinatorial delays 4-input function: f/g inputs to x/y outputs t ilo 0.19 0.40 0.42 0.47 ns, max 5-input function: f/g inputs to f5 output t if5 0.36 0.76 0.8 0.9 ns, max 5-input function: f/g inputs to x output t if5x 0.35 0.74 0.8 0.9 ns, max 6-input function: f/g inputs to y output via f6 mux t if6y 0.35 0.74 0.9 1.0 ns, max 6-input function: f5in input to y output t f5iny 0.04 0.11 0.20 0.22 ns, max incremental delay routing through transparent latch to xq/yq outputs t ifnctl 0.27 0.63 0.7 0.8 ns, max by input to yb output t byyb 0.19 0.38 0.46 0.51 ns, max sequential delays ff clock clk to xq/yq outputs t cko 0.34 0.78 0.9 1.0 ns, max latch clock clk to xq/yq outputs t cklo 0.40 0.77 0.9 1.0 ns, max setup and hold times before/after clock clk 4-input function: f/g inputs t ick / t cki 0.39 / 0 0.9 / 0 1.0 / 0 1.1 / 0 ns, min 5-input function: f/g inputs t if5ck / t ckif5 0.55 / 0 1.3 / 0 1.4 / 0 1.5 / 0 ns, min 6-input function: f5in input t f5inck / t ckf5in 0.27 / 0 0.6 / 0 0.8 / 0 0.8 / 0 ns, min 6-input function: f/g inputs via f6 mux t if6ck / t ckif6 0.58 / 0 1.3 / 0 1.5 / 0 1.6 / 0 ns, min bx/by inputs t dick / t ckdi 0.25 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min ce input t ceck / t ckce 0.28 / 0 0.55 / 0 0.7 / 0 0.7 / 0 ns, min sr/by inputs (synchronous) t rck / t ckr 0.24 / 0 0.46 / 0 0.52 / 0 0.6 / 0 ns, min clock clk minimum pulse width, high t ch 0.56 1.2 1.3 1.4 ns, min minimum pulse width, low t cl 0.56 1.2 1.3 1.4 ns, min set/reset minimum pulse width, sr/by inputs t rpw 0.94 1.9 2.1 2.4 ns, min delay from sr/by inputs to xq/yq outputs (asynchronous) t rq 0.39 0.8 0.9 1.0 ns, max toggle frequency (mhz) (for export control) f tog - 416 400 357 mhz notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time.
virtex ? -e 1.8 v extended memory field programmable gate arrays module 3 of 4 www.xilinx.com ds025-3 (v2.3.2) march 14, 2003 12 1-800-255-7778 r figure 2: detailed view of virtex-e slice by f5in sr clk ce bx yb y yq xb x xq g4 g3 g2 g1 f4 f3 f2 f1 cin 0 1 1 0 f5 f5 ds022_05_092000 cout cy d ce q d ce q f6 ck wso wsh we a4 by dg bx di di o we i3 i2 i1 i0 lut cy i3 i2 i1 i0 o di we lut init init rev rev
virtex ? -e 1.8 v extended memory field programmable gate arrays ds025-3 (v2.3.2) march 14, 2003 www.xilinx.com module 3 of 4 1-800-255-7778 13 r clb arithmetic switching characteristics setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. precise values are provided by the timing analyzer. description (1) symbol speed grade units min -8 -7 -6 combinatorial delays f operand inputs to x via xor t opx 0.32 0.68 0.8 0.8 ns, max f operand input to xb output t opxb 0.35 0.65 0.8 0.9 ns, max f operand input to y via xor t opy 0.59 1.07 1.4 1.5 ns, max f operand input to yb output t opyb 0.48 0.89 1.1 1.3 ns, max f operand input to cout output t opcyf 0.37 0.71 0.9 1.0 ns, max g operand inputs to y via xor t opgy 0.34 0.72 0.8 0.9 ns, max g operand input to yb output t opgyb 0.47 0.78 1.2 1.3 ns, max g operand input to cout output t opcyg 0.36 0.60 0.9 1.0 ns, max bx initialization input to cout t bxcy 0.19 0.36 0.51 0.57 ns, max cin input to x output via xor t cinx 0.27 0.50 0.6 0.7 ns, max cin input to xb t cinxb 0.02 0.04 0.07 0.08 ns, max cin input to y via xor t ciny 0.26 0.45 0.7 0.7 ns, max cin input to yb t cinyb 0.16 0.28 0.38 0.43 ns, max cin input to cout output t byp 0.05 0.10 0.14 0.15 ns, max multiplier operation f1/2 operand inputs to xb output via and t fandxb 0.10 0.30 0.35 0.39 ns, max f1/2 operand inputs to yb output via and t fandyb 0.28 0.56 0.7 0.8 ns, max f1/2 operand inputs to cout output via and t fandcy 0.17 0.38 0.46 0.51 ns, max g1/2 operand inputs to yb output via and t gandyb 0.20 0.46 0.55 0.7 ns, max g1/2 operand inputs to cout output via and t gandcy 0.09 0.28 0.30 0.34 ns, max setup and hold times before/after clock clk cin input to ffx t cckx /t ckcx 0.47 / 0 1.0 / 0 1.2 / 0 1.3 / 0 ns, min cin input to ffy t ccky /t ckcy 0.49 / 0 0.92 / 0 1.2 / 0 1.3 / 0 ns, min notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time.
virtex ? -e 1.8 v extended memory field programmable gate arrays module 3 of 4 www.xilinx.com ds025-3 (v2.3.2) march 14, 2003 14 1-800-255-7778 r clb distributed ram switching characteristics description (1) symbol speed grade units min -8 -7 -6 sequential delays clock clk to x/y outputs (we active) 16 x 1 mode t shcko16 0.67 1.38 1.5 1.7 ns, max clock clk to x/y outputs (we active) 32 x 1 mode t shcko32 0.84 1.66 1.9 2.1 ns, max shift-register mode clock clk to x/y outputs t reg 1.25 2.39 2.9 3.2 ns, max setup and hold times before/after clock clk f/g address inputs t as /t ah 0.19 / 0 0.38 / 0 0.42 / 0 0.47 / 0 ns, min bx/by data inputs (din) t ds /t dh 0.44 / 0 0.87 / 0 0.97 / 0 1.09 / 0 ns, min sr input (we) t ws /t wh 0.29 / 0 0.57 / 0 0.7 / 0 0.8 / 0 ns, min clock clk minimum pulse width, high t wph 0.96 1.9 2.1 2.4 ns, min minimum pulse width, low t wpl 0.96 1.9 2.1 2.4 ns, min minimum clock period to meet address write cycle time t wc 1.92 3.8 4.2 4.8 ns, min shift-register mode minimum pulse width, high t srph 1.0 1.9 2.1 2.4 ns, min minimum pulse width, low t srpl 1.0 1.9 2.1 2.4 ns, min notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time. figure 3: dual-port block selectram web enb rstb clkb addrb[#:0] dib[#:0] wea ena rsta clka addra[#:0] dia[#:0] doa[#:0] dob[#:0] ramb4_s#_s# ds022_06_121699
virtex ? -e 1.8 v extended memory field programmable gate arrays ds025-3 (v2.3.2) march 14, 2003 www.xilinx.com module 3 of 4 1-800-255-7778 15 r block ram switching characteristics tbuf switching characteristics jtag test access port switching characteristics description (1) symbol speed grade units min-8-7-6 sequential delays clock clk to dout output t bcko 0.63 2.46 3.1 3.5 ns, max setup and hold times before clock clk addr inputs t back /t bcka 0.42 / 0 0.9 / 0 1.0 / 0 1.1 / 0 ns, min din inputs t bdck /t bckd 0.42 / 0 0.9 / 0 1.0 / 0 1.1 / 0 ns, min en input t beck /t bcke 0.97 / 0 2.0 / 0 2.2 / 0 2.5 / 0 ns, min rst input t brck /t bckr 0.9 / 0 1.8 / 0 2.1 / 0 2.3 / 0 ns, min wen input t bwck /t bckw 0.86 / 0 1.7 / 0 2.0 / 0 2.2 / 0 ns, min clock clk minimum pulse width, high t bpwh 0.6 1.2 1.35 1.5 ns, min minimum pulse width, low t bpwl 0.6 1.2 1.35 1.5 ns, min clka -> clkb setup time for different ports t bccs 1.2 2.4 2.7 3.0 ns, min notes: 1. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time. description symbol speed grade units min -8 -7 -6 combinatorial delays in input to out output t io 0.0 0.0 0.0 0 .0 ns, max tri input to out output high-impedance t off 0.05 0.092 0.10 0.11 ns, max tri input to valid data on out output t on 0.05 0.092 0.10 0.11 ns, max description symbol value units tms and tdi setup times before tck t ta p t k 4.0 ns, min tms and tdi hold times after tck t tcktap 2.0 ns, min output delay from clock tck to output tdo t tcktdo 11.0 ns, max maximum tck clock frequency f tck 33 mhz, max
virtex ? -e 1.8 v extended memory field programmable gate arrays module 3 of 4 www.xilinx.com ds025-3 (v2.3.2) march 14, 2003 16 1-800-255-7778 r virtex-e pin-to-pin output parameter guidelines all devices are 100% functionally tested. listed below are representative values for typical pin locations and normal clock loading. values are expressed in nanoseconds unless otherwise noted. global clock input to output delay for lvttl, 12 ma, fast slew rate, with dll global clock input to output delay for lvttl, 12 ma, fast slew rate, without dll description (1) symbol device (3) speed grade (2) units min -8 -7 -6 lvttl global clock input to output delay using output flip-flop, 12 ma, fast slew rate, with dll. for data output with different standards, adjust the delays with the values shown in ?? iob output switching characteristics standard adjustments ?? on page 8 . t ickofdll xcv405e 1.0 3.1 3.1 3.1 ns xcv812e 1.0 3.1 3.1 3.1 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 50% v cc threshold with 35 pf external capacitive load. for other i/o standards and different loads, see ta b l e 2 and ta b l e 3 . 3. dll output jitter is already included in the timing calculation. description (1) symbol device speed grade (2) units min -8 -7 -6 lvttl global clock input to output delay using output flip-flop, 12 ma, fast slew rate, without dll. for data output with different standards, adjust the delays with the values shown in ?? iob output switching characteristics standard adjustments ?? on page 8 . t ickof xcv405e 1.6 4.5 4.7 4.9 ns xcv812e 1.8 4.8 5.0 5.2 ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 50% v cc threshold with 35 pf external capacitive load. for other i/o standards and different loads, see ta b l e 2 and ta b l e 3 .
virtex ? -e 1.8 v extended memory field programmable gate arrays ds025-3 (v2.3.2) march 14, 2003 www.xilinx.com module 3 of 4 1-800-255-7778 17 r virtex-e pin-to-pin input parameter guidelines all devices are 100% functionally tested. listed below are representative values for typical pin locations and normal clock loading. values are expressed in nanoseconds unless otherwise noted. global clock set-up and hold for lvttl standard, with dll global clock set-up and hold for lvttl standard, without dll description (1) symbol device (3) speed grade (2) units min-8-7-6 input setup and hold time relative to global clock input signal for lvttl standard. for data input with different standards, adjust the setup time delay by the values shown in ?? iob input switching characteristics standard adjustments ?? on page 6 . no delay t psdll /t phdll xcv405e 1.5 / ? 0.4 1.5 / ? 0.4 1.6 / ? 0.4 1.7 / ? 0.4 ns global clock and iff, with dll xcv812e 1.5 / ? 0.4 1.5 / ? 0.4 1.6 / ? 0.4 1.7 / ? 0.4 ns notes: 1. iff = input flip-flop or latch 2. setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 3. dll output jitter is already included in the timing calculation. description (1) symbol device (3) speed grade (2) units min -8 -7 -6 input setup and hold time relative to global clock input signal for lvttl standard. for data input with different standards, adjust the setup time delay by the values shown in ?? iob input switching characteristics standard adjustments ?? on page 6 . full delay t psfd /t phfd xcv405e 2.3 / 0 2.3 / 0 2.3 / 0 2.3 / 0 ns global clock and iff, without dll xcv812e 2.5 / 0 2.5 / 0 2.5 / 0 2.5 / 0 ns notes: 1. iff = input flip-flop or latch 2. setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is m easured relative to the global clock input signal with the slowest route and heaviest load. 3. a zero ? 0 ? hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed ? best-case ? , but if a ? 0 ? is listed, there is no positive hold time.
virtex ? -e 1.8 v extended memory field programmable gate arrays module 3 of 4 www.xilinx.com ds025-3 (v2.3.2) march 14, 2003 18 1-800-255-7778 r dll timing parameters all devices are 100 percent functionally tested. because of the difficulty in directly measuring many internal timing parameter s, those parameters are derived from benchmark timing patterns. the following guidelines reflect worst-case values across the recommended operating conditions. description symbol f clkin speed grade units -8 -7 -6 min max min max min max input clock frequency (clkdllhf) fclkinhf 60 320 60 320 60 260 mhz input clock frequency (clkdll) fclkinlf 25 160 25 160 25 135 mhz input clock low/high pulse width t dllpw 25 mhz 5.0 5.0 5.0 ns 50 mhz 3.0 3.0 3.0 ns 100 mhz 2.4 2.4 2.4 ns 150 mhz 2.0 2.0 2.0 ns 200 mhz 1.8 1.8 1.8 ns 250 mhz 1.5 1.5 1.5 ns 300 mhz 1.3 1.3 na ns figure 4: dll timing waveforms t clkin t clkin + t iptol period tolerance: the allowed input clock period change in nanoseconds. output jitter: the difference between an ideal reference clock edge and the actual design. _ ds022_24_091200 i deal period actual period + jitter +/- jitter + maximum phase difference phase offset and maximum phase difference + phase offset
virtex ? -e 1.8 v extended memory field programmable gate arrays ds025-3 (v2.3.2) march 14, 2003 www.xilinx.com module 3 of 4 1-800-255-7778 19 r dll clock tolerance, jitter, and phase information all dll output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. revision history the following table shows the revision history for this document. clkdllhf clkdll units description symbol f clkin min max min max input clock period tolerance t iptol - 1.0 - 1.0 ns input clock jitter tolerance (cycle to cycle) t ijitcc - 150 - 300 ps time required for dll to acquire lock (6) t lock > 60 mhz - 20 - 20 s 50 - 60 mhz - - - 25 s 40 - 50 mhz - - - 50 s 30 - 40 mhz - - - 90 s 25 - 30 mhz - - - 120 s output jitter (cycle-to-cycle) for any dll clock output (1) t ojitcc 60 60 ps phase offset between clkin and clko (2) t phio 100 100 ps phase offset between clock outputs on the dll (3) t phoo 140 140 ps maximum phase difference between clkin and clko (4) t phiom 160 160 ps maximum phase difference between clock outputs on the dll (5) t phoom 200 200 ps notes: 1. output jitter is cycle-to-cycle jitter measured on the dll output clock and is based on a maximum tap delay resolution, excluding input clock jitter. 2. phase offset between clkin and clko is the worst-case fixed time difference between rising edges of clkin and clko, excluding output jitter and input clock jitter. 3. phase offset between clock outputs on the dll is the worst-case fixed time difference between rising edges of any two dll outputs, excluding output jitter and input clock jitter. 4. maximum phase difference between clkin an clko is the sum of output jitter and phase offset between clkin and clko, or the greatest difference between clkin and clko rising edges due to dll alone ( excluding input clock jitter). 5. maximum phase difference between clock outputs on the dll is the sum of output jitter and phase offset between any dll clock outputs, or the greatest difference between any two dll output rising edges sue to dll alone ( excluding input clock jitter). 6. add 30% to the value for industrial grade parts. date version revision 03/23/00 1.0 initial xilinx release. 08/01/00 1.1 accumulated edits and fixes. upgrade to preliminary. preview -8 numbers added. reformatted to adhere to corporate documentation style guidelines. minor changes in bg560 pin-out table. 09/19/00 1.2 in table 3 (module 4), fg676 fine-pitch bga ? xcv405e , the following pins are no longer labeled as vref: b7, g16, g26, w26, af20, af8, y1, h1. min values added to virtex-e electrical characteristics tables.
virtex ? -e 1.8 v extended memory field programmable gate arrays module 3 of 4 www.xilinx.com ds025-3 (v2.3.2) march 14, 2003 20 1-800-255-7778 r virtex-e extended memory data sheet the virtex-e extended memory data sheet contains the following modules: ds025-1, virtex-e 1.8v extended memory fpgas: introduction and ordering information (module 1) ds025-2, virtex-e 1.8v extended memory fpgas: functional description (module 2) ds025-3, virtex-e 1.8v extended memory fpgas: dc and switching characteristics (module 3) ds025-4, virtex-e 1.8v extended memory fpgas: pinout tables (module 4) 11/20/00 1.3 updated speed grade -8 numbers in virtex-e electrical characteristics tables (module 3). updated minimums in table 11 (module 2), and added notes to table 12 (module 2). added to note 2 of absolute maximum ratings (module 3). changed all minimum hold times to ? 0.4 for global clock set-up and hold for lvttl standard, with dll (module 3). revised maximum t dllpw in -6 speed grade for dll timing parameters (module 3). 04/02/01 1.4 in ta b le 4 , fg676 fine-pitch bga ? xcv405e , pin b19 is no longer labeled as vref, and pin g16 is now labeled as vref. updated values in virtex-e switching characteristics tables. converted data sheet to modularized format. see the virtex-e extended memory data sheet section. 04/19/01 1.5 updated values in virtex-e switching characteristics tables. 07/23/01 1.6 under absolute maximum ratings , changed (t sol ) to 220 c . changes made to sstl symbol names in iob input switching characteristics standard adjustments table. 07/26/01 1.7 removed t sol parameter and added footnote to absolute maximum ratings table. 09/18/01 1.8 reworded power supplies footnote to absolute maximum ratings table. 10/25/01 1.9 updated the speed grade designations used in data sheets, and added table 1 , which shows the current speed grade designation for each device. updated power-on power supply requirements table. 11/09/01 2.0 updated the xcv405e device speed grade designation to preliminary in ta ble 1 . updated power-on power supply requirements table. 02/01/02 2.1 updated footnotes to the dc input and output levels and dll clock tolerance, jitter, and phase information tables. 07/17/02 2.2 data sheet designation upgraded from preliminary to production. removed mention of mil-m-38510/605 specification. added link to xapp158 from the power-on power supply requirements section. 09/10/02 2.3 revised v in in absolute maximum ratings table. added clock clk switching characteristics to ?? iob input switching characteristics ?? on page 5 and ?? iob output switching characteristics, figure 1 ?? on page 7 . 12/22/02 2.3.1 added footnote regarding v in pci compliance to absolute maximum ratings table. 03/14/03 2.3.2 under power-on power supply requirements , the fastest ramp rate is no longer a "suggested" rate. date version revision

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